Prior art multi-processor computing systems have typically used a shared bus between its one or more processors and a memory controller. FIG. 1 shows a traditional multi-processor prior art computing system. According to the depiction of FIG. 1, the shared bus 105 is a “shared medium” component in which electrical signals passed between any processor and any other processor and/or the memory controller 103 are carried over the same electrical wiring.
The shared bus 105 becomes a bottleneck, particularly for multi-processor systems, because there tends to be heavy communication over the shared bus 105 (through small communicative sessions called “transactions”) between the processors 101_1 through 101_8 and the memory controller 103. In order to improve the performance of multi-processor systems, a new architecture has emerged (which may be referred to as “link based”) in which the shared bus is replaced with a network having point-to-point links between the processors and memory controller.
FIG. 2 shows an example. Here, note that the caching agents 201_1 through 201_8 and memory controller 203 are communicatively coupled by a network 205 having point-to-point links between these components. For ease of drawing the point-to-point links are depicted as being bi-directional. Typically, however, these bi-directional point-to-point links are actually implemented with a pair of unidirectional point-to-point links directed in opposite directions with respect to one another. According to the architecture of FIG. 2, a “caching agent” is a unit containing one or more processing cores (e.g., one or more units of logic circuitry that executes program code) that may have associated cache 202_1 through 202_8 for its respective processing cores. In order to access the system memory 204, a caching agent issues a memory request to a home agent 210 of the memory controller 203. The “home agent” of the memory controller 203 is responsible for maintaining coherency of the transactions that the memory controller deals with over network 205. Alternatively, the home agent 210 may be separate from the memory controller 203.
Note that the architecture shown in FIG. 2 may have different number of caching agents and different number of home agents. To simplify the illustration, FIG. 2 only shows one home agent.
Of interest in these systems are the transactions that occur over the network 205 between the caching agents 201_1 through 201_8 and home agent 210 (e.g., to effect coherent caching and shared access to the system memory for data and/or instructions). The cornerstone of a source snoop broadcast protocol that does not use negative acknowledgement is the pre-allocation of tracker resources at the home agent. The tracker resources may be a multiple-entry structure that is used to keep “track” of the state of these transactions. Each entry may represent a tracker. According to this protocol, pre-allocation requires that a caching agent is allocated a tracker prior to sending a memory access request to the home agent. Static partitioning of the trackers divides the trackers into groups. Each group is reserved exclusively for a particular caching agent. To accommodate all outstanding coherent requests from the various caching agents in a multiprocessor configuration, the resulting tracker size (i.e., the number of trackers) in the home agent can be considerably large; or alternatively, the number of requests from each caching agent has to be limited. Either scenario is sub-optional from a performance point of view. Furthermore, the requirement of pre-allocation coupled with static partitioning of the trackers exasperates the tracker size issue.